1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a junctionless field-effect transistor having an ultra-thin low-crystalline-silicon channel and fabrication method thereof.
2. Description of the Related Art
A conventional field effect transistor, as shown in FIG. 1, is a MOSFET having a MOS structure as a Metal (gate electrode)-Oxide (gate dielectric layer)-Silicon (channel region) structure, consisting of source 210 and drain 220 regions formed by implanting with a dopant of a second conductive type (e.g., n-type) in a silicon substrate 100 of a first conductive type (e.g., p-type) and a gate electrode 400 being separated by a gate dielectric layer 300 and located over a channel region between the source and drain regions.
In the conventional field effect transistor mentioned above, junctions 120 can be come into being due to the source 210 and drain 220 regions formed by a dopant implantation and the junctions form a depletion region (not shown) by pn junctions.
By the being of the depletion regions, a voltage applied to the source and drain electrodes 500 and 600 can generate a current only flowing through a channel formed below the gate electrode 400. Namely, there is an effect being insulated by the depletion regions between the source region 210 and the other part of the silicon substrate 100 as a body region and between the drain region 220 and the body region.
However, there are some problems by the being of the depletion regions. It is a problem that a leakage current is induced in the depletion region formed on the side of the drain region by an impact ionization due to the collision of hot carriers or by the generation of electron-hole pairs due to the tunneling occurred in the overlapping part of the gate electrode and the drain region by a voltage difference between the gate electrode and the drain electrode. Also, it is another problem that the operation of a high frequency such as a cut-off frequency or a power transmission maximum frequency and the like is restricted by the being of the depletion region.
To solve the problems of the conventional MOSFET structure, U.S. Pat. No. 8,026,521B1 and U.S. Patent Publication No. 2010/0276662A1 disclose field effect transistors having a junctionless structure without forming the source/drain regions.
The junctionless field effect transistors developed so far, as shown in FIG. 2, are generally formed in a silicon-on-insulator (SOI) substrate having a buried oxide (BOX) 110 for blocking the leakage current, an active region being a single-crystal silicon layer 200 topped on the BOX 110 of the SOI substrate, and have a structure of source and drain electrodes 500 and 600 contacted directly on the single-crystal silicon layer 200 in both ends of a gate electrode 400 without additional formation of the source/drain regions.
However, because the SOI substrate is 10 to 20 times more expensive than a general bulk silicon substrate, the commercialization of the junctionless field effect transistor (JLFET) as a memory or logic semiconductor device is difficult.
To overcome the above problem, this inventor has already developed a fabrication method of a junctionless field effect transistor using a bulk silicon substrate for substituting an expensive SOI substrate with other inventors and obtained Korean Patent No. 10-1431774. As shown in FIG. 3, Korean Patent No. 10-1431774 discloses a compound junctionless field effect transistor enabled to form a blocking semiconductor layer 130 between a bulk silicon substrate 100 and an active layer 230 by a semiconductor material having a specific difference of energy bandgap from that of the active layer to substitute a buried oxide 110 of an SOI substrate for blocking a leakage current at the off-operation time, and to form the active layer 230 by a semiconductor layer having electron or hole mobility higher than that of silicon to operate perfectly though the doping concentration of the active layer is much lower.
However, Korean Patent No. 10-1431774 has difficult processes for forming a blocking semiconductor layer 130 by a first semiconductor material on a bulk silicon substrate 100, an active layer 230 by a second semiconductor material and the like because the processes should be performed by a heterojunction method under the proper conditions.